The present invention relates to a semiconductor device of Silicon On Insulator (SOI) structure in which a soft error is hard to be produced.
An example of the conventional semiconductor device is set forth in JP-A-2-90535 (laid open on Mar. 30, 1990). A bipolar transistor disclosed therein is a lateral bipolar transistor of a Silicon-On-Insulator (SOI) structure, and has a sectional structure similar to that shown in FIG. 1. Namely, an n-type emitter region 311, a p-type base region 312, an n-type collector region 313, and an n-type collector lead region 314 of a high concentration are provided on an insulating substrate 100 so as to reduce parasitic capacitance and aim at a high speed. In this transistor structure, an island including regions 311, 312, 313 and 314 is formed, and separation among elements can be realized easily by arranging islands so as to separate them from one another on the insulating substrate.
In a device shown in FIG. 1, however, an emitter electrode 301, a base electrode 302 and a collector electrode 303 are formed so as to cover opening portions in a silicon oxide film 150 provided on the n-type emitter region 311, the p-type base region 312 and the n-type collector lead region 314 of high concentration, respectively. Therefore, mask alignment tolerance between respective regions and opening portions and mask alignment tolerance between opening portions and electrodes are required, and an influence by electrode processing dimensions (line width and space) is also exerted. As a result, it has been impossible to perform fine patterning of above-mentioned electrode pattern (301, 302, 303) and the like. Thus, it has been difficult to miniaturize a transistor. Moreover, it has been difficult to reduce widths of the n-type emitter region 311, the n-type collector region 313 and the n-type collector lead region 314 of high concentration because of similar reasons, which prevents operation at a high speed.